Publicação: Experimental comparison between relaxed and strained Ge pFinFETs
dc.contributor.author | Oliveira, A. V. | |
dc.contributor.author | Agopian, P. G. D. [UNESP] | |
dc.contributor.author | Martino, J. A. | |
dc.contributor.author | Simoen, E. | |
dc.contributor.author | Mitard, J. | |
dc.contributor.author | Witters, L. | |
dc.contributor.author | Collaert, N. | |
dc.contributor.author | Claeys, C. | |
dc.contributor.author | Sarafis, P. | |
dc.contributor.author | Nassiopoulou, A. G. | |
dc.contributor.institution | Universidade de São Paulo (USP) | |
dc.contributor.institution | Universidade Estadual Paulista (Unesp) | |
dc.contributor.institution | Imec | |
dc.contributor.institution | Univ Ghent | |
dc.contributor.institution | Katholieke Univ Leuven | |
dc.date.accessioned | 2018-11-26T15:47:29Z | |
dc.date.available | 2018-11-26T15:47:29Z | |
dc.date.issued | 2017-01-01 | |
dc.description.abstract | The experimental comparison between relaxed and strained Ge pFinFETs operating at room temperature is discussed. Although, the strain into the channel improves the drain current for wide transistors due to the boost of hole mobility, the gate stack engineering has to be further studied in order to solve the threshold voltage shift. The relaxed channel achieves a lower subthreshold swing compared to the strained one, since the latter presents a higher source/drain leakage current. Considering a figure of merit for analog applications, i.e., intrinsic voltage gain AV, no relevant difference between the relaxed and strained channel performances has been shown for short devices while the relaxed ones present a higher Av for longer devices. | en |
dc.description.affiliation | Univ Sao Paulo, LSI PSI EPUSP, Sao Paulo, Brazil | |
dc.description.affiliation | UNESP, Sao Joao Da Boa Vista, Brazil | |
dc.description.affiliation | Imec, Leuven, Belgium | |
dc.description.affiliation | Univ Ghent, Dept Solid St Sci, Ghent, Belgium | |
dc.description.affiliation | Katholieke Univ Leuven, ESAT, EE, Leuven, Belgium | |
dc.description.affiliationUnesp | UNESP, Sao Joao Da Boa Vista, Brazil | |
dc.description.sponsorship | Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) | |
dc.description.sponsorship | Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) | |
dc.description.sponsorship | Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) | |
dc.description.sponsorship | FWO | |
dc.format.extent | 180-183 | |
dc.identifier.citation | 2017 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis 2017). New York: Ieee, p. 180-183, 2017. | |
dc.identifier.issn | 2330-5738 | |
dc.identifier.lattes | 0496909595465696 | |
dc.identifier.orcid | 0000-0002-0886-7798 | |
dc.identifier.uri | http://hdl.handle.net/11449/160099 | |
dc.identifier.wos | WOS:000425210900048 | |
dc.language.iso | eng | |
dc.publisher | Ieee | |
dc.relation.ispartof | 2017 Joint International Eurosoi Workshop And International Conference On Ultimate Integration On Silicon (eurosoi-ulis 2017) | |
dc.rights.accessRights | Acesso aberto | pt |
dc.source | Web of Science | |
dc.subject | FinFET | |
dc.subject | germanium | |
dc.subject | p-type | |
dc.subject | strained | |
dc.subject | relaxed | |
dc.title | Experimental comparison between relaxed and strained Ge pFinFETs | en |
dc.type | Trabalho apresentado em evento | pt |
dcterms.license | http://www.ieee.org/publications_standards/publications/rights/rights_policies.html | |
dcterms.rightsHolder | Ieee | |
dspace.entity.type | Publication | |
unesp.author.lattes | 0496909595465696[2] | |
unesp.author.orcid | 0000-0002-0886-7798[2] | |
unesp.campus | Universidade Estadual Paulista (UNESP), Faculdade de Engenharia, São João da Boa Vista | pt |