Experimental behavior of Line-TFET applied to Low-Dropout Voltage Regulator

Abstract

This work presents the design of Low Dropout Voltage Regulator (LDO) with Line-Tunnel Field Effect Transistor (Line-TFET), in which the transistor was modeled using Verilog-A and Lookup Table (LUT) obtained from experimental data. The LDO was designed with gm/ID of 9.6 V-1, a load current (IL) of 1 mA, source voltage (VDD) of 2.3 V and 500 mV of dropout voltage (VDO). For comparison, a MOSFET LDO was designed with 130 nm MOSFET PDK. Despite of the lower Gain-BandWidth Product (GBW), the Line-TFET LDO presents better results like 0.18 V/A of load regulation, 0.01 mV/V of line regulation thanks to its high loop gain with a 78% efficiency. Also, it was observed that Line-TFET LDO can be designed without the compensation capacitor to reach stability.