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Analysis of omega-gate nanowire soi mosfet under analog point of view

dc.contributor.authorPerina, Welder F.
dc.contributor.authorMartino, João A.
dc.contributor.authorAgopian, Paula G. D. [UNESP]
dc.contributor.institutionUniversidade de São Paulo (USP)
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.date.accessioned2020-12-12T01:26:49Z
dc.date.available2020-12-12T01:26:49Z
dc.date.issued2020-01-01
dc.description.abstractThis paper presents an evaluation of omega-gate nanowire n-and p-type SOI MOSFETs performance focusing on the main analog figures of merit, like saturation transcon-ductance (gmsat), output conductance (gD), transconductance over drain current (gm/IDS) ratio, Early voltage (VEA), intrinsic gain (AV) and unit gain frequency (ft). The different channel widths (WNW) and channel lengths (L) were also evaluated. These devices presented values of subthreshold slope near the theoretical limit at room temperature (60 mV/dec), and in the worst case, a DIBL value smaller than 70 mV/V. Showing its immunity to short channel effects (SCEs) in the studied channel length range. The narrowest device showed great electrostatic coupling, improving gm, presenting an unit gain frequency over 200 GHz and intrinsic voltage gain over 80 dB. These values suggests that this device is capable of achieving good performance on new applications such as 5G communications and In-ternet-of-Things (IoT).en
dc.description.affiliationLSI/PSI/USP University of São Paulo
dc.description.affiliationUNESP São Paulo State University
dc.description.affiliationUnespUNESP São Paulo State University
dc.description.sponsorshipCoordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)
dc.description.sponsorshipConselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
dc.description.sponsorshipFundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)
dc.identifierhttp://dx.doi.org/10.29292/jics.v15i1.113
dc.identifier.citationJournal of Integrated Circuits and Systems, v. 15, n. 1, 2020.
dc.identifier.dimensionspub.1127969790
dc.identifier.doi10.29292/jics.v15i1.113
dc.identifier.issn1872-0234
dc.identifier.issn1807-1953
dc.identifier.orcid0000-0002-0886-7798
dc.identifier.orcid0000-0001-8121-6513
dc.identifier.orcid0000-0001-6205-351X
dc.identifier.scopus2-s2.0-85086123912
dc.identifier.urihttp://hdl.handle.net/11449/198960
dc.language.isoeng
dc.publisherJournal of Integrated Circuits and Systems
dc.relation.ispartofJournal of Integrated Circuits and Systems
dc.rights.accessRightsAcesso abertopt
dc.rights.sourceRightsoa_all
dc.rights.sourceRightsgold
dc.sourceScopus
dc.sourceDimensions
dc.subjectIntrinsic Voltage Gain
dc.subjectNanowire
dc.subjectOmega-gate
dc.subjectSOI MOSFET
dc.subjectUnit-gain Frequency
dc.titleAnalysis of omega-gate nanowire soi mosfet under analog point of viewen
dc.typeArtigopt
dspace.entity.typePublication

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