Low frequency noise performance of horizontal, stacked and vertical silicon nanowire MOSFETs
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Data
2021-10-01
Autores
Simoen, Eddy
de Oliveira, Alberto Vinicius
Agopian, Paula Ghedini Der [UNESP]
Ritzenthaler, Romain
Mertens, Hans
Horiguchi, Naoto
Martino, Joao Antonio
Claeys, Cor
Veloso, Anabela
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Resumo
The low frequency noise performance of Gate-All-Around Nanowire (NW) or Nanosheet (NS) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) is investigated, taking account of the impact of the device architecture, i.e., junctionless (JL) versus inversion-mode (IM) and process variations for the gate metal. The horizontal devices are characterized by 1/f noise, dominated by the number fluctuation mechanism, so that the power spectral density (PSD) is directly proportional with the trap density in the gate stack. The average 1/f noise PSD is becoming smaller going from single NW transistors on Silicon-on-Insulator substrates, to stacked horizontal NS devices on bulk silicon and, finally, vertical NWFETs with a substrate source contact. At low currents and frequencies below 1 kHz the 1/f noise in the vertical NWs is, in contrast to the horizontal devices, controlled by mobility fluctuations. In these devices white noise is observed above 1 kHz.
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Palavras-chave
Gate-All-Around, Low-frequency noise, Nanosheets, Nanowires, Silicon MOSFETs
Como citar
Solid-State Electronics, v. 184.