A transactional runtime system for the Cell/BE architecture
dc.contributor.author | Baldassin, Alexandro José [UNESP] | |
dc.contributor.author | Goldstein, Felipe | |
dc.contributor.author | Azevedo, Rodolfo | |
dc.contributor.institution | Universidade Estadual Paulista (Unesp) | |
dc.contributor.institution | Universidade Estadual de Campinas (UNICAMP) | |
dc.date.accessioned | 2014-05-20T15:33:24Z | |
dc.date.available | 2014-05-20T15:33:24Z | |
dc.date.issued | 2012-12-01 | |
dc.description.abstract | Single-core architectures have hit the end of the road and industry and academia are currently exploiting new multicore design alternatives. In special, heterogeneous multicore architectures have attracted a lot of attention but developing applications for such architectures is not an easy task due to the lack of appropriate tools and programming models. We present the design of a runtime system for the Cell/BE architecture that works with memory transactions. Transactional programs are automatically instrumented by the compiler, shortening development time and avoiding synchronization mistakes usually present in lock-based approaches (such as deadlock). Experimental results conducted with a prototype implementation and the STAMP benchmark show good scalability for applications with moderate to low contention levels, and whose transactions are not too small. For those cases in which a small performance loss is admissible, we believe that the ease of programming provided by transactions greatly pays off. (C) 2012 Elsevier B.V. All rights reserved. | en |
dc.description.affiliation | Univ Estadual Paulista, UNESP, Rio Claro, Brazil | |
dc.description.affiliation | Univ Estadual Campinas, UNICAMP, Campinas, SP, Brazil | |
dc.description.affiliationUnesp | Univ Estadual Paulista, UNESP, Rio Claro, Brazil | |
dc.description.sponsorship | IBM | |
dc.description.sponsorship | Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq) | |
dc.description.sponsorship | Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) | |
dc.description.sponsorshipId | FAPESP: 11/19373-6 | |
dc.format.extent | 1535-1546 | |
dc.identifier | http://dx.doi.org/10.1016/j.jpdc.2012.08.001 | |
dc.identifier.citation | Journal of Parallel and Distributed Computing. San Diego: Academic Press Inc. Elsevier B.V., v. 72, n. 12, p. 1535-1546, 2012. | |
dc.identifier.doi | 10.1016/j.jpdc.2012.08.001 | |
dc.identifier.issn | 0743-7315 | |
dc.identifier.uri | http://hdl.handle.net/11449/42030 | |
dc.identifier.wos | WOS:000310669600001 | |
dc.language.iso | eng | |
dc.publisher | Academic Press Inc. Elsevier B.V. | |
dc.relation.ispartof | Journal of Parallel and Distributed Computing | |
dc.relation.ispartofjcr | 1.815 | |
dc.relation.ispartofsjr | 0,502 | |
dc.rights.accessRights | Acesso restrito | |
dc.source | Web of Science | |
dc.subject | Multiprocessors | en |
dc.subject | Parallel programming | en |
dc.subject | Transactional memory | en |
dc.title | A transactional runtime system for the Cell/BE architecture | en |
dc.type | Artigo | |
dcterms.license | http://www.elsevier.com/about/open-access/open-access-policies/article-posting-policy | |
dcterms.rightsHolder | Academic Press Inc. Elsevier B.V. | |
unesp.author.lattes | 4738829911864396[1] | |
unesp.author.orcid | 0000-0001-8824-3055[1] | |
unesp.campus | Universidade Estadual Paulista (Unesp), Instituto de Geociências e Ciências Exatas, Rio Claro | pt |
unesp.department | Estatística, Matemática Aplicada e Computação - IGCE | pt |
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