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Run Time Power and Accuracy Management with Approximate Circuits

dc.contributor.authorElaraby, Nahla
dc.contributor.authorFrismuth, David
dc.contributor.authorFilho, Nilson Neves [UNESP]
dc.contributor.authorJantsch, Axel
dc.contributor.institutionTu Wien
dc.contributor.institutionCanadian International College-CIC
dc.contributor.institutionUniversidade Estadual Paulista (UNESP)
dc.date.accessioned2023-07-29T12:38:51Z
dc.date.available2023-07-29T12:38:51Z
dc.date.issued2022-01-01
dc.description.abstractThe ever-expanding need for low-power devices can be approached by implementing approximate computing methods. A restrictive energy budget is met by dropping the concept of fully exact or entirely deterministic computations. We propose a methodology to trade off accuracy with run-time power consumption through Dynamic Partial Reconfiguration (DPR) of Field Programmable Gate Arrays (FPGAs). Optimization is done by switching between predefined design configurations and combining exact and approximate versions of the most power-consuming circuit blocks. We designed a dynamic reconfiguration manager to select and configure the FPGA with the appropriate partial bitstream. The reconfiguration is executed automatically at run time according to the system power state and the accuracy requirement of the running application. The experimental results show that the proposed mechanism can achieve between 10% and 58% power reduction with a maximum error of 0.35 and an average error range of 0.1 beside negligible reconfiguration energy cost.en
dc.description.affiliationTu Wien
dc.description.affiliationCanadian International College-CIC
dc.description.affiliationUnesp
dc.description.affiliationUnespUnesp
dc.identifierhttp://dx.doi.org/10.1109/VLSI-SoC54400.2022.9939639
dc.identifier.citationIEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, v. 2022-October.
dc.identifier.doi10.1109/VLSI-SoC54400.2022.9939639
dc.identifier.issn2324-8440
dc.identifier.issn2324-8432
dc.identifier.scopus2-s2.0-85142459949
dc.identifier.urihttp://hdl.handle.net/11449/246361
dc.language.isoeng
dc.relation.ispartofIEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
dc.sourceScopus
dc.subjectApproximate Computing
dc.subjectFPGA
dc.subjectRun time Power
dc.titleRun Time Power and Accuracy Management with Approximate Circuitsen
dc.typeTrabalho apresentado em evento

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