Readout circuit design using experimental data of line-TFET devices

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By considering the analog characteristics of Line Tunneling Field Effect Transistors (Line-TFETs) that are suitable for small-signal amplification, this paper studies the design of a readout circuit with these devices while making comparisons with conventional MOSFET designs. The results show that the Line-TFET design exhibits high gain and low reading error (51dB open loop gain) while using a simple one-stage amplifier and results in a huge reduction in circuit area by using pseudo feedback resistors that have their differential resistance increased for smaller dimensions, achieving up to 50Gohm in a 120nm x 100nm device. This enables cutoff frequencies below 1Hz while using nanometer devices and smaller capacitors. Moreover, the readout circuit achieves 33nW of power consumption even though the Line-TFET devices are not biased in the subthreshold regime.



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ECS Transactions, v. 97, n. 5, p. 165-170, 2020.