On the impact of mode transition on phased transactional memory performance
dc.contributor.author | Munoz Morales, Catalina | |
dc.contributor.author | Honorio, Bruno | |
dc.contributor.author | de Carvalho, Joao P.L. | |
dc.contributor.author | Baldassin, Alexandro [UNESP] | |
dc.contributor.author | Araujo, Guido | |
dc.contributor.institution | Universidade Estadual de Campinas (UNICAMP) | |
dc.contributor.institution | Universidade Estadual Paulista (UNESP) | |
dc.contributor.institution | University of Alberta | |
dc.date.accessioned | 2023-07-29T13:35:26Z | |
dc.date.available | 2023-07-29T13:35:26Z | |
dc.date.issued | 2023-03-01 | |
dc.description.abstract | Several transactional memory implementations that employ state-of-the-art software and hardware techniques to deliver performance have been investigated in the last decade. Phased-based Transactional Memory (PhTM) systems run transactions in phases, such that all transactions in a phase execute in the same (hardware/software) mode. In PhTM, a runtime monitors the execution and decides when to change all transactions to another execution mode. Identifying the right moment to perform a mode transition is a central problem to achieve performance in PhTM systems. This article analyzes PhTM and provides a characterization of mode transitions and their impact on performance. We consider three PhTM implementations: (i) PhTM*, the first phased-based TM designed; (ii) Commit Throughput Measurement (CTM), a general-purpose runtime; and (iii) GoTM, a Graph-oriented runtime. We conduct a performance analysis to identify the drawbacks and benefits of each PhTM implementation with respect to their associated parameters. Results with speedups of up to 10× over the sequential baseline for CTM show that this mechanism generally shows better performance for a diverse set of applications. | en |
dc.description.affiliation | University of Campinas (UNICAMP) Institute of Computing, Av. Albert Einstein, 1251 Cidade Universitária, Sao Paulo | |
dc.description.affiliation | Univ. Estadual Paulista (UNESP) DEMAC, Avenida 24 A, 1515, Sao Paulo | |
dc.description.affiliation | University of Alberta Department of Computing Science, 2-32 Athabasca Hall | |
dc.description.affiliationUnesp | Univ. Estadual Paulista (UNESP) DEMAC, Avenida 24 A, 1515, Sao Paulo | |
dc.description.sponsorship | Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP) | |
dc.description.sponsorshipId | FAPESP: 2017/15236-0 | |
dc.description.sponsorshipId | FAPESP: 2019/04536-9 | |
dc.format.extent | 126-139 | |
dc.identifier | http://dx.doi.org/10.1016/j.jpdc.2022.11.009 | |
dc.identifier.citation | Journal of Parallel and Distributed Computing, v. 173, p. 126-139. | |
dc.identifier.doi | 10.1016/j.jpdc.2022.11.009 | |
dc.identifier.issn | 0743-7315 | |
dc.identifier.scopus | 2-s2.0-85145558234 | |
dc.identifier.uri | http://hdl.handle.net/11449/248135 | |
dc.language.iso | eng | |
dc.relation.ispartof | Journal of Parallel and Distributed Computing | |
dc.source | Scopus | |
dc.subject | Hardware transactional memory | |
dc.subject | Software transactional memory | |
dc.title | On the impact of mode transition on phased transactional memory performance | en |
dc.type | Artigo |