On the impact of mode transition on phased transactional memory performance

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dc.contributor.authorMunoz Morales, Catalina
dc.contributor.authorHonorio, Bruno
dc.contributor.authorde Carvalho, Joao P.L.
dc.contributor.authorBaldassin, Alexandro [UNESP]
dc.contributor.authorAraujo, Guido
dc.contributor.institutionUniversidade Estadual de Campinas (UNICAMP)
dc.contributor.institutionUniversidade Estadual Paulista (UNESP)
dc.contributor.institutionUniversity of Alberta
dc.date.accessioned2023-07-29T13:35:26Z
dc.date.available2023-07-29T13:35:26Z
dc.date.issued2023-03-01
dc.description.abstractSeveral transactional memory implementations that employ state-of-the-art software and hardware techniques to deliver performance have been investigated in the last decade. Phased-based Transactional Memory (PhTM) systems run transactions in phases, such that all transactions in a phase execute in the same (hardware/software) mode. In PhTM, a runtime monitors the execution and decides when to change all transactions to another execution mode. Identifying the right moment to perform a mode transition is a central problem to achieve performance in PhTM systems. This article analyzes PhTM and provides a characterization of mode transitions and their impact on performance. We consider three PhTM implementations: (i) PhTM*, the first phased-based TM designed; (ii) Commit Throughput Measurement (CTM), a general-purpose runtime; and (iii) GoTM, a Graph-oriented runtime. We conduct a performance analysis to identify the drawbacks and benefits of each PhTM implementation with respect to their associated parameters. Results with speedups of up to 10× over the sequential baseline for CTM show that this mechanism generally shows better performance for a diverse set of applications.en
dc.description.affiliationUniversity of Campinas (UNICAMP) Institute of Computing, Av. Albert Einstein, 1251 Cidade Universitária, Sao Paulo
dc.description.affiliationUniv. Estadual Paulista (UNESP) DEMAC, Avenida 24 A, 1515, Sao Paulo
dc.description.affiliationUniversity of Alberta Department of Computing Science, 2-32 Athabasca Hall
dc.description.affiliationUnespUniv. Estadual Paulista (UNESP) DEMAC, Avenida 24 A, 1515, Sao Paulo
dc.description.sponsorshipFundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)
dc.description.sponsorshipIdFAPESP: 2017/15236-0
dc.description.sponsorshipIdFAPESP: 2019/04536-9
dc.format.extent126-139
dc.identifierhttp://dx.doi.org/10.1016/j.jpdc.2022.11.009
dc.identifier.citationJournal of Parallel and Distributed Computing, v. 173, p. 126-139.
dc.identifier.doi10.1016/j.jpdc.2022.11.009
dc.identifier.issn0743-7315
dc.identifier.scopus2-s2.0-85145558234
dc.identifier.urihttp://hdl.handle.net/11449/248135
dc.language.isoeng
dc.relation.ispartofJournal of Parallel and Distributed Computing
dc.sourceScopus
dc.subjectHardware transactional memory
dc.subjectSoftware transactional memory
dc.titleOn the impact of mode transition on phased transactional memory performanceen
dc.typeArtigo

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Artigos - Estatistica, Matemática Aplicada e Computação - IGCE