Publicação:
Two-stage amplifier design based on experimental Line-Tunnel FET data

dc.contributor.authorFilho, Walter Gonçalez
dc.contributor.authorMartino, Joao A.
dc.contributor.authorRangel, Roberto
dc.contributor.authorAgopian, Paula G. D. [UNESP]
dc.contributor.authorSimoen, Eddy
dc.contributor.authorRooyackers, Rita
dc.contributor.authorClaeys, Cor
dc.contributor.authorCollaert, Nadine
dc.contributor.institutionUniversidade de São Paulo (USP)
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.contributor.institutionImec
dc.contributor.institutionClaRoo
dc.contributor.institutionKu Leuven
dc.date.accessioned2021-06-25T10:22:49Z
dc.date.available2021-06-25T10:22:49Z
dc.date.issued2019-10-14
dc.description.abstractThis work presents for the first time a two-stage operational transconductance amplifier (OTA) design based on experimental Line-TFET devices. To account for different parasitic effects, make the project more feasible and avoid complicated and inaccurate analytical modelling, experimental devices are measured and the data is used in lookup tables to be coded in Verilog-A hardware description language. A two-stage amplifier is designed considering the particularities of these devices and the figures of merit achieved are related to its characteristics, including the non-idealities verified in the experimental characterization. The designed amplifier exhibits extremely high open loop voltage gain, good performance and bandwidth when compared with other TFET designs, at moderate power supply voltage with high output swing and low power consumption. The results obtained are compared with MOSFET designs and with other TFET based amplifiers found in the literature.en
dc.description.affiliationLSI/PSI/USP University of Sao Paulo
dc.description.affiliationUnesp Sao Paulo State University
dc.description.affiliationImec
dc.description.affiliationClaRoo
dc.description.affiliationE.E. Dept Ku Leuven
dc.description.affiliationUnespUnesp Sao Paulo State University
dc.identifierhttp://dx.doi.org/10.1109/S3S46989.2019.9320637
dc.identifier.citation2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019.
dc.identifier.doi10.1109/S3S46989.2019.9320637
dc.identifier.scopus2-s2.0-85100867443
dc.identifier.urihttp://hdl.handle.net/11449/205885
dc.language.isoeng
dc.relation.ispartof2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2019
dc.sourceScopus
dc.subjectanalog circuit design
dc.subjectLine-TFET
dc.subjecttwo-stage amplifier
dc.titleTwo-stage amplifier design based on experimental Line-Tunnel FET dataen
dc.typeTrabalho apresentado em evento
dspace.entity.typePublication

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