Experimental analysis of differential pairs designed with line tunnel FET devices

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dc.contributor.authorMartino, M. D.V.
dc.contributor.authorMartino, J. A.
dc.contributor.authorAgopian, P. G.D. [UNESP]
dc.contributor.authorRooyackers, R.
dc.contributor.authorSimoen, E.
dc.contributor.authorCollaert, N.
dc.contributor.authorClaeys, C.
dc.contributor.institutionUniversidade de São Paulo (USP)
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.contributor.institutionImec
dc.contributor.institutionKU Leuven
dc.date.accessioned2018-12-11T16:53:34Z
dc.date.available2018-12-11T16:53:34Z
dc.date.issued2018-03-07
dc.description.abstractThe aim of this work is to study, for the first time, the behavior of differential pair circuits designed with Line TFETs and compare the suitability of this technology with alternatives such as FinFETs and Point TFETs. The first part highlights experimental characteristics of individual Line TFET transistors, which present similar transconductance and better output conductance when compared to FinFETs, while revealing better transconductance and worse output conductance in comparison to Point TFETs. Next, the experimental data for Line TFET differential pairs is presented for different bias conditions and dimensions. The last part compares the intrinsic voltage gain (Ad), the compliance voltage and susceptibility to channel length mismatch for the 3 technologies. It is explained that Line TFET presents the highest Ad, FinFETs provides a wider operation region and Point TFETs are the least susceptible to channel length variations.en
dc.description.affiliationLSI/PSI/USP University of Sao Paulo
dc.description.affiliationSao Paulo State University (UNESP) Campus Sao Joao da Boa Vista
dc.description.affiliationImec
dc.description.affiliationE.E. Dept KU Leuven
dc.description.affiliationUnespSao Paulo State University (UNESP) Campus Sao Joao da Boa Vista
dc.format.extent1-3
dc.identifierhttp://dx.doi.org/10.1109/S3S.2017.8308756
dc.identifier.citation2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, v. 2018-March, p. 1-3.
dc.identifier.doi10.1109/S3S.2017.8308756
dc.identifier.lattes0496909595465696
dc.identifier.orcid0000-0002-0886-7798
dc.identifier.scopus2-s2.0-85047754688
dc.identifier.urihttp://hdl.handle.net/11449/171062
dc.language.isoeng
dc.relation.ispartof2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017
dc.rights.accessRightsAcesso restrito
dc.sourceScopus
dc.subjectdifferential gain
dc.subjectDifferential Pair
dc.subjectdimensions mismatch
dc.subjectFinFET
dc.subjectLine TFET
dc.subjectPoint TFET
dc.titleExperimental analysis of differential pairs designed with line tunnel FET devicesen
dc.typeTrabalho apresentado em evento
unesp.author.lattes0496909595465696[3]
unesp.author.orcid0000-0002-0886-7798[3]

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