Pros and cons of symmetrical dual-k spacer technology in hybrid FinFETs

Abstract

The symmetrical dual-k spacer technology in hybrid FinFETs has been widely explored for better electrostatic control of the fin-based devices in nanoscale region. Since, high-k tangible spacer materials are broadly became a matter of study due to their better immunity to the short channel effects (SCEs) in nano devices. However, the only cause that restricts the circuit designers from using high-k spacer is the unreasonable increasing fringing capacitances. This work quantitatively analyzed the benefits and drawbacks of considering two different dielectric spacer materials symmetrically in either sides of the channel for the hybrid device. From the demonstrated results, the inclusion of high-k spacer predicts an effective reduction in off-state leakage along with an improvement in drive current. However, these devices have paid the cost in terms of a high total gate-to-gate capacitance (Cgg) that consequently results poor cutoff frequency (fT) and delay.