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Proton-irradiation influence on current mirror circuit using verilog-a approach based on experimental SOI FinFET characteristics

dc.contributor.authorDe Sousa, Bruna Ramos
dc.contributor.authorAgopian, Paula Ghedini Der [UNESP]
dc.contributor.authorMartino, Joao Antonio
dc.contributor.institutionUniversidade de São Paulo (USP)
dc.contributor.institutionUniversidade Estadual Paulista (Unesp)
dc.date.accessioned2020-12-12T01:25:42Z
dc.date.available2020-12-12T01:25:42Z
dc.date.issued2020-04-01
dc.description.abstractIn this work, a simple methodology is proposed to simulate the current mirror circuit based on the triple-gate SOI FinFET experimental data, called lookup table in Verilog-A. It was analyzed the reliability of the model, comparing between experimental and simulated data, with has proven to be reliable. It was also evaluated the performance of the transistor and as well the circuit regarding the efficiency and the gain, for p- and n-types, based on three different fin widths, before and after proton-irradiation.en
dc.description.affiliationLSI/PSI/USP University of Sao Paulo
dc.description.affiliationUNESP Sao Paulo State University
dc.description.affiliationUnespUNESP Sao Paulo State University
dc.description.sponsorshipCoordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES)
dc.description.sponsorshipConselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)
dc.description.sponsorshipFundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)
dc.format.extent171-177
dc.identifierhttp://dx.doi.org/10.1149/09705.0171ecst
dc.identifier.citationECS Transactions, v. 97, n. 5, p. 171-177, 2020.
dc.identifier.doi10.1149/09705.0171ecst
dc.identifier.issn1938-5862
dc.identifier.issn1938-6737
dc.identifier.lattes0496909595465696
dc.identifier.orcid0000-0002-0886-7798
dc.identifier.scopus2-s2.0-85085865710
dc.identifier.urihttp://hdl.handle.net/11449/198924
dc.language.isoeng
dc.relation.ispartofECS Transactions
dc.sourceScopus
dc.titleProton-irradiation influence on current mirror circuit using verilog-a approach based on experimental SOI FinFET characteristicsen
dc.typeTrabalho apresentado em evento
dspace.entity.typePublication
unesp.author.lattes0496909595465696[2]
unesp.author.orcid0000-0002-0886-7798[2]

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