Temperature influence on analog figures-of-merit of nanosheet nMOSFET devices for sub-7nm technology node

Abstract

This work analyzes the impact of temperature on the Analog figures of Merit of vertically stacked nanosheet nMOSFETs. The excellent electrostatic control between gate and channel results in a strong reduction of the short channel effect, as expected. The analog parameters like the intrinsic voltage gain, transistor efficiency and Early voltage are analyzed as a function of temperature. A high intrinsic voltage gain and a weak temperature dependence are observed, mainly at strong inversion region. The transistor efficiency and subthreshold swing maintain their value close to the theoretical limit.