Trade-off analysis between gm/ID and fT of nanosheet NMOS transistors with different metal gate stack at high temperature
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2022-05-01
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In this work the gate-all-around nanosheet transistor is analyzed at high temperatures, from analog point of view. At first, the gate-all-around nanosheet (NS) behavior is compared with reported omega-gate nanowire (NW) transistors, at room temperature. It is worth noting that the nanosheets devices present a stronger electrostatic coupling between gate and channel (lower short channel effect -SCE), and higher intrinsic voltage gain, AV (better Early voltage) when compared with NW devices (60 dB for NS and 55 db for NW, with L = 200 nm). Therefore, the second part of this work focuses on the analog study only for NS transistors (with different metal gate stacks), presenting the trade-off between transistor efficiency and unit gain frequency, fT from room temperature to 200 °C. The obtained results are very promising for both gate stack transistors, where values of transistor efficiency about 37 V−1 (T = 25 °C and L = 200 nm) and fT about 260 GHz (T = 25 °C and L = 28 nm) are obtained. The optimal application point was obtained at the transition from moderate to strong inversion.
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Analog operation, FT, High temperature, Intrinsic voltage gain, MOSFET, Nanosheet (NS), Nanowire (NW), Transistor efficiency
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Solid-State Electronics, v. 191.